serial presence detect rev. 0.4 jan. 2001 184pin unbuffered dimm rev. 0.4 184pin unbuffered dimm spd specification(128mb b-die base) jan. 2001 revision 0.0 (december 1999) 1. first release for internal use only. revision 0.1 (february 2000) 1. first edition for external release. revision 0.2 (april 2000) 1. byte 9, byte10 : add tcc and tac at cl=2.5 in a0 ( ddr200@cl=2)and a2(ddr266@cl=2). 2. byte 23, bte24 : add tcc and tac at cl=2 in b0 ( ddr266@cl=2.5). revision 0.3 (june 2000) 1. byte 85 : changed pcb revision from t0 to t1. revision 0.4 ( jan 2001) 1. byte 30 : changed tras of b0 from 48ns to 45ns.
serial presence detect rev. 0.4 jan. 2001 184pin unbuffered dimm M381L3313BT1-ca0/b0/a2 ? organization : 32mx72 ? composition : 16mx8 *9*2 ? used component part # : k4h280838b-tca0/b0/a2 ? # of rows in module : 2 row ? # of banks in component : 4 banks ? feature : 1,250 mil height & double sided component ? refresh : 4k/64ms ? bin sort : a0 ( ddr200@cl=2),b0 ( ddr266@cl=2.5), a2(ddr266@cl=2) ? contents : byte # function described function supported hex value note a0 b0 a2 a0 b0 a2 0 defines # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k-bit) 08h 2 fundamental memory type sdram ddr 07h 3 # of row address on this assembly 12 0ch 1 4 # of column address on this assembly 10 0ah 1 5 # of module rows on this assembly 2 row 02h 6 data width of this assembly 72 bits 48h 7 .........data width of this assembly - 00h 8 vddq and interface standard of this assembly sstl 2.5v 04h 9 ddr sdram cycle time at cas latency =2.5 8ns 7.5ns 7ns 80h 75h 70h 2 10 ddr sdram access time from clock at cl=2.5 0. 8ns 0.75n 0.75n 80h 75h 75h 2 11 dimm configuration type(non-parity, parity, ecc) ecc 02h 12 refresh rate & type 15.6us & self refresh 80h 13 primary ddr sdram width x8 08h 14 error checking ddr sdram data width x8 08h 15 minimum clock delay for back-to-back random column address tccd=1clk 01h 16 ddr sdram device attributes : burst lengths supported 2,4,8 0eh 17 ddr sdram device attributes : # of banks on each ddr sdram 4 banks 04h 18 ddr sdram device attributes : cas latency supported 2, 2.5 0ch 19 ddr sdram device attributes : cs latency 0clk 01h 20 ddr sdram device attributes : we latency 1clk 02h 21 ddr sdram module attributes registered address& control inputs and on-card dll 20h 22 ddr sdram device attributes : general +/-0.2v voltage tolerance 00h 23 ddr sdram cycle time at cl =2 10ns 10ns 7.5ns a0h a0h 75h 2 24 ddr sdram access time from clock at cl =2 0.8ns 0.75n 0.75 80h 75h 75h 2 25 ddr sdram cycle time at cl =1.5 - - - 00h 2 26 ddr sdram access time from clock at cl =1.5 - - - 00h 2 27 minimum row precharge time (=trp) 20ns 20ns 20ns 50h 50h 50h 28 minimum row activate to row active delay(=trrd) 15ns 15ns 15ns 3ch 3ch 3ch 29 minimum ras to cas delay(=trcd) 20ns 20ns 20ns 50h 50h 50h 30 minimum active to precharge time(=tras) 48ns 45ns 45ns 30h 2dh 2dh 31 module row density 128mb 20h 32 command and address signal input setup time 1.1ns 0.9ns 0.9ns b0h 90h 90h 33 command and address signal input hold time 1.1ns 0.9ns 0.9ns b0h 90h 90h 34 data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h
serial presence detect rev. 0.4 jan. 2001 184pin unbuffered dimm serial presence detect information byte # function described function supported hex value note a0 b0 a2 a0 b0 a2 35 data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h 36-61 superset information (may be used in future) - 00h 62 spd data revision code initial release 00h 63 checksum for bytes 0 ~ 62 - 33h afh 7fh 64 manufacturer jedec id code samsung ceh 65 - 71 ....... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (memory module) m 4dh 74 manufacturer part # (dimm configuraion) 3 33h 75 manufacturer part # (data bits & module type) blank 20h 76 ....... manufacturer part # (data bits & module type) 8 38h 77 ....... manufacturer part # (data bits & module type) 1 31h 78 manufacturer part # (operating voltage) l 4ch 79 manufacturer part # (module depth) 3 33h 80 manufacturer part # (module depth) 3 33h 81 manufacturer part # (refresh, # of rows in comp.&interface) 1 31h 82 manufacturer part # (composition component) 3 33h 83 manufacturer part # (component revision) b-die 42h 84 manufacturer part # (package type) t 54h 85 manufacturer part # (pcb revision) 1 31h 86 manufacturer part # (hyphen) "-" 2dh 87 manufacturer part # (power) c 43h 88 manufacturer part # (minimum cycle time) a b a 41h 42h 41h 89 manufacturer part # (minimum cycle time) 0 0 2 30h 30h 32h 90 manufacturer part # (t.b.d) blank 20h 91 manufacturer revison code (for pcb) 0 30h 92 manufacturer revison code (for component) b-die 42h 93 manufacturing date (week) - - 3 94 manufacturing date (year) - - 3 95~98 assembly serial # - - 4 99~127 manufacturer specific data (may be used in future) undefined 00h 5 128~255 open for customer use undefined 00h 5 1. the bank select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. 5. these bytes are undefined and coded with ?00h? . note :
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